Typically, an Integrated Circuit (IC) consists of a number of supply pins (power and ground), a number of input signal pins and some output pins. All of those pins (also referred to herein as pads) need safe electrostatic discharge (ESD) protection paths to all the other pins of the integrated circuit. In the IC industry, many different protection concepts exist, which include heterogeneous types of ESD protection for different pin types on a single IC. Various approaches have been utilized to provide ESD protection for the output pins of an IC, each with particular advantages and disadvantages. An output driver is typically created by an inverter-type of circuit. ESD protection of output drivers is extremely difficult. Many techniques exist all with drawbacks and disadvantages, such as time delay, and silicon consuming trigger voltage tuning, area, complexity, speed reduction, among other notable deficiencies.
FIG. 1 is a schematic diagram of a conventional CMOS output driver 100 consisting of an inverter stage 102 comprising a first transistor 104 and a second transistor 106. Depending on the logic state of the input node 108 (driven by the core circuit 110), the output potential is pulled either high to Vdd (PMOS conduction) or low to Vss (NMOS conduction). In particular, the inverter circuit 102 comprises at least one PMOS transistor 104 and at least one NMOS transistor 106 coupled together (i.e., formed in a stack), illustratively between a first voltage line, Vdd, and a second voltage line, Vss. The internal core circuit 110 of the integrated circuit manipulates an input node 108 (gate connection of the NMOS and PMOS transistors 104, 106) of the inverter 102 to communicate with other chips or logic at the outside of the integrated circuit. For a logic low signal voltage at the input node, the NMOS transistor 106 will be switched off, while the PMOS transistor 104 will conduct and bring the output node close to the Vdd potential. In an instance where a logical high is present at the input node 108, the NMOS transistor 106 will conduct, thereby pulling the output node low, while the PMOS transistor 104 is switched off.
When positive ESD stress is applied at an unprotected output pad 112 versus the Vss line or ground, the NMOS transistor 106 will first conduct a small amount of current in MOS mode, due to an uncontrolled or floating NMOS gate. If no special ‘keep-off’ circuitry is behind the NMOS gate, such as described in commonly assigned U.S. Pat. No. 6,529,359, the contents of which is incorporated herein by reference, the gate is typically pulled high due to the parasitic gate-drain capacitance. This parasitic or dynamic gate-biasing reduces the snapback trigger voltage Vt1 to a Vt1′, as shown in FIG. 2. This will create a MOS channel in the NMOS transistor 106 which reduces the Vt1 trigger voltage. Consequently, the NMOS transistor 106 will more easily trigger into a (parasitic) bipolar mode. A low gate bias is enough to reduce the Vt1 trigger voltage to the holding voltage of the parasitic NPN device.
One approach to providing ESD protection is to prevent snapback in the NMOS transistor 106 in the output driver 100. One conventional protection concept shown as circuit 300 in FIG. 3 consists of ‘dual diode’ protection of the output node, connecting a diode 304 between the Vss or ground node and the output node (diode down) and connecting a diode 302 between the output node and the Vdd node (diode up). These diodes 302/304 redirect ESD current to the supply lines/busses. A power clamp 306 between the Vdd and Vss lines clamps the voltage between the supply lines and dissipates the ESD current.
FIG. 3 depicts a schematic diagram of a dual diode and power clamp protection circuit 300 for ESD protection of the output driver 102. Two competitive trigger paths exist for the positive stress between the output pad and Vss. The intended current path flows through the diode 302 from output to Vdd and the power clamp 306 to the grounded Vss node. Due to a floating gate of the NMOS transistor 106, the transistor triggers into snapback at a reduced trigger voltage Vt1˜Vh. In many high voltage technologies, this causes damage to the NMOS transistor. However, in many other technologies, such as, but not limited to, advanced silicided technologies, triggering into snapback can be dangerous as well. If the NMOS transistor is not ballasted to ensure uniform conduction through the entire NMOS, damage may result. In all cases, it will lead to a failure if the NMOS is not robust enough to shunt large ESD currents.
Furthermore, the total voltage drop in the intended current path can become very high due to a large bus resistance (large distance to a power clamp), a resistive diode (typical for high voltage technologies) or a high resistive power clamp. When this total voltage drop in the intended current path is too high, the current path through the NMOS transistor 106 can trigger, stressing the NMOS transistor 106 into a bipolar mode. When the NMOS transistor 106 is not designed for bipolar conduction, this leads to destruction of the NMOS transistor. Due to the reduced trigger voltage of the NMOS (Vt1′<Vt1, see above and FIG. 2), the maximum or critical voltage for the intended current path can be relatively small in advanced CMOS technologies.
Special techniques exist to increase the Vt1 trigger voltage of the NMOS transistor by pulling the NMOS gate to Vss during ESD stress. Such ‘keep-off circuits’ have been described before (U.S. Pat. No. 6,529,359) and can be used to protect the NMOS transistor. However, those circuits increase the complexity of the pre-driver logic and only increase the critical voltage a small amount (typically 1–2V in advanced CMOS technologies: Vdelta=Vavalanche−Vhold). NMOS destruction can still occur for larger ESD stress currents.
The isolation resistor 308 ‘Riso’ (see FIG. 3) that is sometimes placed between the output pad 112 and the output driver 102 can reduce the current through the NMOS transistor 106. If a small part of the ESD current flows through the NMOS transistor 106 and the resistor 308, a large voltage drop is induced that favors the intended current path through the diode 302 and the power clamp 306. This isolation resistor 308 has been used in mature technologies as a “quick” ESD fix, but it has many drawbacks. A large resistance value (˜50 Ohm to 1 kOhm) is needed to effectively reduce the current through the NMOS transistor 106 to safe values. The output driver speed and output current/voltage is reduced as a function of the resistance value. Thus, the output driver size needs to be increased to maintain the normal operation output current level constant. Such an increase in size may not be practical.
Because the bus resistance typically increases the total voltage drop to excessive values, another method exists which locally protects the NMOS transistor 106. A local clamp 318/320 is placed near and parallel to the drain-source of the NMOS. The intention is to clamp the voltage to a safe value below the (reduced) Vt1 (Vt1′) trigger voltage of the NMOS transistor 106. This requires a cumbersome trigger voltage selection for the local clamp 318/320 due to a very narrow ESD design window. The clamp needs to start conduction at a voltage well below the Vt1/Vt1′ trigger voltage (which defines the maximum trigger voltage) of the NMOS transistor, but well above the normal operation maximum signal voltage to prevent unwanted triggering (which defines the minimum trigger voltage). In many applications, the difference between the maximum and minimum voltage is very small and sometimes negative. As such, in many instances, use of a local clamp 318/320 is not useful in protecting the transistors of any output driver inverter 102.
Presently, available techniques for protecting an output driver from ESD events are complex and interfere with the normal operation of the output driver. Therefore, there is a need in the art for a method and apparatus to improve the protection of the transistors used in output drivers.